Samsung released HBM3E memory samples with a speed of 9.8Gbps and plans to launch HBM4 in 2025

According to news from this website on October 12, according to Samsung’s official blog, HBM memory for high-performance computing (HPC) has ushered in new progress. will develop 9.8Gbps HBM3E products and has begun to provide samples to customers.

In addition, HBM4 memory is being developed with a target of 2025. In order to be suitable for this product, NCF assembly technology and HCB technology optimized for high-temperature thermal characteristics are being prepared.

Note on this site: NCF (Non-conductive Film): a polymer layer (Polymer layer) used to protect the solid joint (Solder joint) between laminated chips from insulation and mechanical impact ).

HCB (hybrid bonding) is a new generation of bonding technology that uses copper (conductor) and oxide film (insulator) for bonding instead of traditional welding

At the beginning of this year, Samsung’s AVP (Advanced Packaging) business team was established to strengthen cutting-edge packaging technology and maximize synergy among business units. Samsung plans to provide cutting-edge custom packaging services with HBM, including 2.5D and 3D cutting-edge packaging solutions.

Samsung said that high-end central processing units used for artificial intelligence services need to have more than 100 cores, and each core needs to have enough memory. In addition, in order to load more capacity into the limited package space, process technology to minimize the size of a dynamic random access memory (DRAM) single chip, and design technology to correctly place components within the form factor and ensure operation according to specifications are also very important. IMPORTANT

Samsung released 32Gb DDR5 DRAM memory last month. Through architectural improvements of the same package size, twice the capacity of 16Gb DRAM is achieved, and 128GB modules can be manufactured without using the TSV process. Samsung said this innovation makes it possible to reduce costs and increase productivity, while also reducing power consumption by 10%

TSV (Through Silicon Via, through silicon via): a packaging technology that can make chips thinner , drill hundreds of small holes and connect electrodes that pass vertically through the holes in the top and bottom chips.

Samsung officials stated at the end of their blog that they will continue to overcome technical limitations and develop a variety of memory solution products that are unprecedented in the world in the future. In particular, Samsung plans to develop ultra-high-performance, ultra-high-capacity, and ultra-low-power memory products in the AI ​​era based on processes below 10 nanometers, claiming that "it will be a major inflection point in the DRAM market."

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