144-core, 3D-stacked SRAM: Fujitsu details next-generation data center processor MONAKA

This website reported on July 28 that according to foreign media TechRader, Fujitsu introduced in detail the FUJITSU-MONAKA (hereinafter referred to as MONAKA) processor planned to be shipped in 2027. MONAKA CPU is based on the "cloud native 3D many-core" architecture and adopts the Arm instruction set. It is oriented to the data center, edge and telecommunications fields. It is suitable for AI computing and can implement mainframe-level RAS1.

Fujitsu said that MONAKA will achieve a leap in energy efficiency and performance:

1. Thanks to technologies such as ultra-low voltage (ULV) process, the CPU can achieve 2 times the energy efficiency of competing products in 2027, and cooling does not require water cooling ；
2. In addition, the application performance of this processor can also reach 2 times that of its opponents.

In terms of instructions, the vector instruction set equipped with MONAKA has been upgraded to SVE2, which can better meet the needs of the AI ​​and HPC fields; in addition, the CPU also adds support for confidential secure computing.

MONAKA supports dual-socket, each CPU contains 144 Armv9 architecture cores.

Each CPU includes a central IO Die and four 3D vertically stacked complexes. The bottom is a silicon interposer (Si Interposer) and packaging layer that connects various parts;

Each complex is processed by The processor core Core Die is combined with the LLC last-level cache SRAM Die. The Core Die is located above the SRAM Die.

MONAKA’s Core Die is based on the 2nm process, while the lower SRAM Die and the central IO Die are built on the more mature 5nm process.

Fujitsu said that the 2nm part of its processor only accounts for 30% of the overall die area, helping to achieve better cost-effectiveness.

Since the on-chip 3D stacked SRAM cache can already provide excellent bandwidth, the MONAKA processor abandoned the HBM memory used by the previous generation product - the A64FX used in the "Fuyue" supercomputer - for off-chip storage, and adopted More traditional 12-channel DDR5 memory .

The processor also provides PCIe 6.0 lanes and supports CXL 3.0 interconnect.

▲ Comparison with A64FX Note on this site: 1RAS is the abbreviation for Reliability, Availability and Serviceability.

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