How to Create a Simple C Makefile for a Single-File Project?

How to Make a SIMPLE C Makefile

Problem:
We need to create a Makefile to manage our C project, but we haven't been taught how to do so. The project consists of a single file, a3driver.cpp, that imports a class from /user/cse232/Examples/example32.sequence.cpp.

Solution:

1. Basic Makefile:

a3a.exe: a3driver.cpp example32.sequence.cpp
    g++ -g -o a3a.exe a3driver.cpp example32.sequence.cpp

This Makefile states that the executable a3a.exe depends on the source files a3driver.cpp and example32.sequence.cpp. When executed, it will execute the command to compile the program into the executable file.

2. Using Built-in Rules:

CC=g++
CPPFLAGS=-g

a3a.exe: a3driver.o example32.sequence.o
    $(CC) $(LDFLAGS) -o a3a.exe a3driver.o example32.sequence.o

a3driver.o: a3driver.cpp
    $(CC) $(CPPFLAGS) -c a3driver.cpp

example32.sequence.o: example32.sequence.cpp
    $(CC) $(CPPFLAGS) -c example32.sequence.cpp

This Makefile utilizes built-in rules to simplify the compilation commands. It defines the CC variable as the C compiler, and the CPPFLAGS variable with common compilation flags. The dependencies are still explicitly defined, but the compilation commands are automatically generated.

3. Using Auto-generated Dependencies:

CC=g++
CPPFLAGS=-g

a3a.exe: a3driver.o example32.sequence.o
    $(CC) $(LDFLAGS) -o a3a.exe a3driver.o example32.sequence.o

depend: .depend

.depend: $(SRCS)
    $(CC) $(CPPFLAGS) -MM $^ > .depend;

.PHONY: clean

clean:
    rm -f a3driver.o example32.sequence.o .depend

include .depend

This Makefile uses the built-in -MM flag to automatically generate dependencies. The depend target executes the command that generates the file .depend with the dependencies. The .PHONY: clean target is a special target that is not actually a file or rule. The clean target removes the object files and the .depend file.

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