How Do I Escape Expression Interpolation in Makefiles to Execute Commands Correctly?

Escaping Expression Interpolation in Makefiles

When writing Makefiles, it's common to want to execute commands that incorporate expressions. A common example of this is in testing, where you might want to run tests selectively based on certain criteria.

Suppose you're working on a Go project and want to exclude tests from the vendor directory. You could easily do this in the command line using:

$ go test $(go list ./... | grep -v /vendor/)

However, when you try to incorporate this into a Makefile:

test:
    go test $(go list ./... | grep -v /vendor/)

.PHONY: test

You'll notice that the expression is not interpolated:

$ make
go test
?       github.com/m90/some-repo    [no test files]

To resolve this issue, you need to escape the "$" character in the expression using a second "$":

test:
    go test $$(go list ./... | grep -v /vendor/)

.PHONY: test

By escaping the "$", you're instructing the Makefile to interpret the expression as a literal command to be executed, rather than trying to substitute the variable.

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