News indicates that the number of EUV exposure layers of Samsung Electronics’ 2nm process has increased by more than 30%, and the SF1.4 node is expected to exceed 30 layers in the future.

According to news from this website on July 23, Korean media The Elec reported on the 17th of this month that the 2nm advanced process Samsung Electronics is expected to launch next year will increase the number of EUV exposure layers by more than 30% compared to the existing 3nm process, reaching "20~ The middle and second half of 30.” Korean media mentioned in the report that depending on the nature of the product, even the number of exposed layers at the same node is not completely fixed. However, overall, the average number of EUV exposure layers in Samsung Electronics' 3nm process is only 20; in the SF1.4 process, which is expected to be mass-produced in 2027, the number of EUV exposure layers is expected to exceed 30 layers.

▲ ASML’s new generation 0.33NA EUV lithography machine NXE:3800E With the evolution of advanced processes, the requirements for transistor size have become increasingly stringent. Using EUV lithography to replace traditional DUV in the exposure layer can achieve higher lithography accuracy, further increase transistor density, and accommodate more integrated circuits per unit area.
In this context, advanced logic foundry companies are actively purchasing ASML’s EUV machines.
Take TSMC as an example. According to previous reports on this site, it will receive a total of more than 60 EUV lithography machines this year and next. Korean media estimates that TSMC will have more than 160 EUV lithography machines by the end of 2025.
In addition, the usage of EUV lithography in the DRAM memory industry is also increasing:
On the sixth generation 20~10nm level process (i.e. 1c nm, 1γ nm), Samsung Electronics uses 6~7 EUV layers, and SK Hynix uses 5 EUV layers, Micron also introduced EUV lithography for the first time at this node.

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