TSMC plans to launch the N4C process in 2025, with a cost reduction of up to 8.5% compared to N4P

News from this site on April 26, TSMC recently demonstrated a new 4nm-level production process N4C, further enhanced the 5nm-level production process by significantly reducing costs and optimizing design energy efficiency.

TSMC recently held the 2024 North American Technology Seminar. This site translated the content of Zhang Kaiwen, the company’s vice president of business development, as follows:

Our 5nm and 4nm process cycles are not over yet. From N5 to N4, the optical shrink density has improved by 4%, and we will continue to enhance transistor performance.

We are now introducing the N4C process for our 4nm technology lineup, allowing our customers to eliminate some masks and improve original IP designs such as standard cells and SRAM to further reduce overall product-level cost of ownership.

The N4C process further expands TSMC’s N5/N4 node series lineup and is built on N4P process technology by redesigning standard cells and SRAM cells, changing some design rules and reducing the number of library module layers used can reduce costs by up to 8.5% compared to N4P.

The above is the detailed content of TSMC plans to launch the N4C process in 2025, with a cost reduction of up to 8.5% compared to N4P. For more information, please follow other related articles on the PHP Chinese website!