AMD Zen 5 execution engine exposed: using true 512-bit FPU

According to news from this site on April 5, the source Moore's Law is Dead shared information about the AMD Zen 5 processor execution engine (Execution Engine) in the latest video, saying that it will use a true 512-bit Floating point unit (FPU).

According to the slides shared by the source, Zen 5’s execution engine is described in detail, using a true 512-bit FPU.

AMD Zen 4 processor uses a dual-channel 256-bit FPU when executing AVX-512 instruction workload, while Zen 5 uses a real 512-bit FPU to process 512-bit There will be higher performance in terms of AVX or VNNI instructions.

This site also learned from the report that AMD has upgraded relevant components for the 512-bit FPU, increased the capacity of L1 DTLB, expanded the load-store queue, and doubled the bandwidth of the L1 data cache. Size increased by 50%. The size of L1D has increased from 32 KB in "Zen 4" to 48 KB now.

FPU MADD latency reduced by 1 cycle. In addition to the FPU, AMD has increased the number of Integer execution pipes from 8 (Zen 4) to 10, and the exclusive L2 cache size per core is still 1 MB.

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