Research shows that AMD processors are also affected by the Rowhammer memory attack, and officials provide mitigation measures

News from this site on March 27, according to the latest research by researchers at the Swiss Federal Institute of Technology in Zurich, AMD’s Zen2 to Zen4 architecture processors will also be affected by the Rowhammer memory attack. AMD officials have provided responses and mitigation measures in this regard.

Note from this site: The Rowhammer attack takes advantage of the physical characteristics of modern DRAM memory. By repeatedly reading and writing the memory, it changes the charge state in adjacent memory cells and achieves bit flipping. An attacker can gain access to sensitive data or escalate privileges by inducing bit flips at specific locations.

Rowhammer attacks were previously common on Intel CPUs and Arm architecture processors. On the AMD side, this type of attack is difficult to implement due to the design differences of the memory system.

However, this time the researchers successfully built a Rowhammer attack variant named ZenHammer for AMD processors by reverse engineering AMD’s complex memory addressing functions.

The researchers conducted tests on the Ryzen 5 3600X CPU with Zen2 architecture and the Ryzen 5 5600G APU with Zen3 architecture. The results were ten attempts on these two systems using DDR4 DRAM memory. 7 and 6 successes respectively.

In addition, the researchers also conducted tests on the AMD Zen4 architecture platform using DDR5 memory. As a result, in ten attempts, only one set based on Ryzen 7 7700X processing success on the system.

This shows that the new platform is less susceptible to ZenHammer due to memory support for on-chip ECC, high memory refresh rates, and improved Rowhammer attack mitigation .

Regarding this latest research, AMD issued an announcement, recommending users to contact hardware manufacturers to determine whether they are sensitive to ZenHammer attacks, and gave the following mitigation suggestions:

Use support for ECC DRAM memory

Use a memory refresh rate higher than 1x

Disable memory burst/delayed refresh

For EPYC Xiaolong platforms using DDR4 memory, use the maximum support Activation count (MAC) memory controller;

For EPYC platforms using DDR5 memory, use a memory controller that supports Refresh Management.

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