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2’s complement number system is widely used in computer architecture.
N-bit 2's complement number system can represent numbers from -2n-1 to 2n-1-1
4-bit can represent numbers from (-8 to 7)
5 bits can represent numbers from (-16 to 15) in the 2's complement system.
Overflow occurs in addition when 2 N-bit 2’s complement numbers are appended and the answer is too large to fit in that N-bit group.
The computer contains N-bit fixed registers. The result of adding two N-digit numbers will be the largest N 1-digit number.
The carry flag stores extra bits. But a carry doesn't always indicate an overflow.
When-
the result of adding two negative numbers is a positive number or
The result of adding two negative numbers is a negative number.
Therefore, overflow can be detected by verifying the most significant bit (MSB) of both operands and the result. However, instead of implementing a 3-bit comparator, overflow can be detected by verifying the carry and carry output from the MSB. We consider N-bit addition of 2’s complement numbers.
Overflow occurs when the carry input is not equal to the carry output. The above overflow expression can be discussed from the following analysis.
In the first picture, the most significant bits of the two numbers are 0, indicating that they are positive numbers. Here, if the carry input is 1, we get the most significant bit of the result to be 1, indicating that the result is negative (overflow), and the carry output is 0. Carry in is not equal to carry out, so overflow occurs.
In the second picture, the most significant bits of the two numbers are 1, indicating that they are negative numbers. Here, if the carry input is 0, we get the most significant bit of the result to be 0, indicating that the result is positive (overflow), and the carry output is 1. Carry in is not equal to carry out, so overflow occurs.
Therefore, the MSB carry-in and carry-out are sufficient to detect overflow.
The above XOR gate can be used to detect overflow.
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