How to use make command under linux

How make works
For those who don't know the mechanics behind it, the make command accepts targets just like command line arguments. These targets are usually stored in special files named "makefiles", and the files also contain operations corresponding to the targets. For more information, read this series of articles on how makefiles work.

When the make command is executed for the first time, it scans the makefile to find the target and its dependencies. If these dependencies are themselves targets, continue scanning the makefiles for these dependencies to establish their dependencies, and then compile them. Once the main dependencies are compiled, then the main target is compiled (which is passed in through the make command).

Now, assuming you have modified a certain source file and you execute the make command again, it will only compile the target file related to the source file. Therefore, compiling the final executable file saves a lot of money. time.

make command example
The following is the test environment used in this article:

os —— ubunut 13.04
shell —— bash 4.2.45
application —— gnu make 3.81

The following is the content of the project:

$ ls 
anothertest.c makefile test.c test.h

The following is the makefile Content:

all: test 

test: test.o anothertest.o 
  gcc -wall test.o anothertest.o -o test

test.o: test.c 
  gcc -c -wall test.c 

anothertest.o: anothertest.c 
  gcc -c -wall anothertest.c 

clean: 
  rm -rf *.o test

Now let’s look at some examples of make command applications under linux:

1. A simple example

In order to compile the entire project, you can simply use make or follow the make command with the target all.

$ make 
gcc -c -wall test.c 
gcc -c -wall anothertest.c 
gcc -wall test.o anothertest.o -o test

You can see the dependencies created for the first time by the make command and the actual target.

If you check the directory contents again, there are some more .o files and executable files in it:

$ ls 
anothertest.c anothertest.o makefile test test.c test.h test.o

Now, assuming you have made some modifications to the test.c file, use make to compile the project again :

$ make 
gcc -c -wall test.c 
gcc -wall test.o anothertest.o -o test

You can see that only test.o is recompiled, but the other test.o is not recompiled.

Now clean all the target files and the executable file test, you can use the target clean:

$ make clean
rm -rf *.o test

$ ls
anothertest.c makefile test.c test.h

You can see that all the .o files and the executable file test have been deleted.

2. Pass the -b option to make all targets always rebuild

By now, you may have noticed that the make command does not compile those targets that have been compiled since the last build. There are no changed files, but if you want to override the default behavior of make, you can use the -b option.

The following is an example:

$ make
make: nothing to be done for `all'.

$ make -b
gcc -c -wall test.c
gcc -c -wall anothertest.c
gcc -wall test.o anothertest.o -o test

You can see that although the make command will not compile any files, make -b will force compilation of all target files and the final executable file.

3. Use the -d option to print debugging information

If you want to know what make actually does when it is executed, use the -d option.

Here is an example:

$ make -d | more
gnu make 3.81
copyright (c) 2006 free software foundation, inc.
this is free software; see the source for copying conditions.
there is no warranty; not even for merchantability or fitness for a
particular purpose.

this program built for x86_64-pc-linux-gnu
reading makefiles…
reading makefile `makefile'…
updating makefiles….
considering target file `makefile'.
looking for an implicit rule for `makefile'.
trying pattern rule with stem `makefile'.
trying implicit prerequisite `makefile.o'.
trying pattern rule with stem `makefile'.
trying implicit prerequisite `makefile.c'.
trying pattern rule with stem `makefile'.
trying implicit prerequisite `makefile.cc'.
trying pattern rule with stem `makefile'.
trying implicit prerequisite `makefile.c'.
trying pattern rule with stem `makefile'.
trying implicit prerequisite `makefile.cpp'.
trying pattern rule with stem `makefile'.
--more--

This is a very long output, you also saw that I used the more command to display the output page by page.

4. Use the -c option to change the directory

You can provide a different directory path for the make command, and the directory will be switched before searching for the makefile.

This is a directory, assuming you are in the current directory:

$ ls 
file file2 frnd frnd1.cpp log1.txt log3.txt log5.txt
file1 file name with spaces frnd1 frnd.cpp log2.txt log4.txt

But the makefile file of the make command you want to run is saved in the ../make-dir/ directory, you can Do this:

$ make -c ../make-dir/ 
make: entering directory `/home/himanshu/practice/make-dir' 
make: nothing to be done for `all'. 
make: leaving directory `/home/himanshu/practice/make-dir

You can see that the make command first switches to a specific directory, executes it there, and then switches back.

5. Use the -f option to treat other files as makefiles

If you want to rename the makefile file, such as my_makefile or other names, we If you want make to treat it as a makefile, use the -f option.

make -f my_makefile

With this method, the make command will choose to scan my_makefile instead of makefile.

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