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Can ensure the visibility of shared variables in a multi-threaded environment
Prevent multiple instructions by adding a memory barrier Reordering
Visibility means that when a thread modifies a shared variable, other threads can immediately see the modification. A value, visibility is essentially caused by several aspects
#cpu-level cache, a three-level cache is designed in the CPU to solve the problem of CPU computing efficiency and There is a problem of memory IO efficiency, but it also brings about a problem of cache consistency. In the case of multi-threaded execution, the cache consistency problem will lead to visibility problems. Therefore, for the addition of volatile A modified shared variable of the
keyword, the jvm virtual machine will automatically add a #lock assembly instruction, and this instruction will automatically add a bus lock
or cache according to different CPU models. Lock
The bus lock locks the CPU front-side bus, which results in that at the same time, there can only be One thread communicates with the memory, thus avoiding visibility problems caused by multi-thread concurrency
Cache lock is an optimization of bus lock, because bus lock leads to a large increase in CPU usage efficiency Decline, so the cache lock only locks the target data in the CPU's third-level cache, and the cache lock uses the MESI cache consistency protocol to implement
Instruction reordering instructions are inconsistent in the order of written data and the order of execution, which leads to visibility problems in a multi-threaded environment. Instruction reordering is essentially a means of performance optimization. Instruction reordering Sorting comes from several aspects
The cpu level further optimizes the MESI protocol
to improve CPU utilization. He introduces a called StoreBuffer
is a mechanism, and this optimization mechanism will lead to out-of-order execution of the CPU. In order to avoid such problems, the CPU provides memory barrier instructions. Upper-layer applications can insert memory barriers at appropriate places to avoid CPU instructions. A problem with reordering
During the compilation process, the compiler reasonably reorders the instructions to optimize without changing the single-thread semantics and program correctness. Overall performance, so the volatile
keyword is added to the shared variable, so the compiler level will not trigger optimization of the compiler. At the same time, in the jvm, it will insert memory barrier instructions to avoid reordering problems.
In addition to the volatile
keyword, developed from JDK5, JMM uses a Happens-Before
model to describe multi-thread visibility A relationship, that is, there is a Happens-Before
relationship between two operations, then the two operations have a visibility relationship, and there is no need to consider adding the volatile
keyword. To provide a guarantee of visibility
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