As we continue to approach the limits of Moore's Law, chip interconnects are also in big trouble.

Interconnects — sometimes the nanometer-wide metal lines that connect transistors to circuits on ICs — are in need of an “overhaul.” As chip factories gradually approach the limits of Moore's Law, interconnection is becoming a major bottleneck in the industry.

At the 68th IEEE International Electronic Devices Conference (IEDM) in early December 2022, IBM’s Chris Penny told engineers, “In about 20-25 years, Copper has always been the metal of choice for interconnects. However, the scale of copper is now slowing down, which provides opportunities for alternative conductors."

##According to the IEDM 2022 research report, Ruthenium. ) is the No. 1 candidate, but it's not as simple as swapping one metal for another. The process by which they are formed on the chip must be reversed. These new connections will require different shapes and higher densities, as well as better insulation lest signal-consuming capacitance take away all their advantages.

The location of interconnections is also destined to change, and that change is coming soon. But research is increasingly showing that the benefits of this shift come at a cost.

Ruthenium, top vias and air gaps

Currently, ruthenium is the most popular copper replacement. But research shows that older methods used to build copper interconnects don't work well with ruthenium. Copper interconnects are built using a so-called damascene process. The first chipmakers used photolithography to carve the shapes of interconnects into the dielectric insulation layer above the transistors. They then deposited liner and barrier materials to prevent copper atoms from drifting to other parts of the chip and messing up the entire process. The trench is then filled with copper, often overfilling it, so the excess must be polished away.

Penny told IEDM engineers that all the extra stuff, including pads and barriers, accounts for 40-50% of the interconnect volume. As a result, the conductive portions of the interconnects are narrowing, especially in the ultra-fine vertical connections between interconnect layers, resulting in increased resistance.

But researchers at IBM and Samsung have found a way to build closely spaced, low-resistance ruthenium interconnects without the need for liners or seeds. The process, called spacer assisted litho-etch litho-etch (SALELE), relies on the dual help of extreme ultraviolet lithography. Instead of filling trenches, it etches ruthenium interconnects out of the layer or metal and then fills the gaps with dielectric.

The researchers achieved optimal resistance using ultra-thin, high-density horizontal interconnects, but this added capacitance and lost the benefit. Fortunately, the spaces between the slender ruthenium wires are prone to air ingress because SALELE has constructed vertical connections called vias (i.e. on top of the horizontal connections rather than below), which is currently available The best insulator. For these ultra-thin, high-density interconnects, adding air gaps has huge potential benefits, Penny said, reducing line capacitance by 30 percent. Suffice it to say, SALELE technology provides a roadmap for processes at 1nm and beyond.

PCB board using through-hole routing. Image source: https://www.wevolver.com/article/what-is-a-via-a-comprehensive-guide

buried rail, back power supply technology and 3D chip

Intel plans to completely change the location of the interconnects that power the transistors on the chip, which could happen as early as 2024. The solution, called back-side power delivery, involves moving the power interconnect network beneath the silicon to connect to the transistors from below. This scheme has two main advantages: First, it allows current to pass through wider interconnects with lower resistance, thereby reducing power loss. The second is to make room for signal transmission interconnections above the transistors, which means that the logic cells can be smaller.

At the IEDM2022 conference, Imec researchers proposed some ways to make backside power supply work more efficiently, that is, moving the endpoints of the power supply network (known as buried power rails) to higher close to the transistors without destroying the electronic properties of those transistors. But they also discovered a slightly troubling issue, where the backside power supply can cause heat to build up when used in 3D stacked chips.

But the good news is: When researchers at Imec looked at how much horizontal distance is needed between buried power rails and transistors, the answer was almost zero. Even though additional processing cycles are required to ensure that the transistors are not affected, the researchers say it is possible to build the track next to the transistor channel region—although still tens of nanometers below it. This means that the logic cells may be smaller.

The bad news: In separate research, Imec engineers simulated several versions of the same future CPU. Some have the power network used today, called front-end power, where all interconnects, including data and power, are built in layers on top of the silicon. Others have back-powered networks, one of which is a 3D stack of two CPUs with a back power supply on the bottom and a front power supply on top.

The simulation of 2D CPU verified the superiority of backside power supply. For example, compared with front-side power supply, it reduces the loss of power transmission by half, and the transient voltage drop is not too obvious. More importantly, the CPU area is reduced by 8%. However, the hottest part of the back chip is about 45% hotter than the hottest part of the front chip. This is likely because backside powering requires the chip to be thinned enough that it needs to be bonded to a separate piece of silicon for stability. This bond blocks the flow of heat.

The real problem lies in the 3D IC. The top CPU has to get power from the bottom CPU, but the long transfer to the top creates some problems. While the voltage drop characteristics of the bottom CPU are still better than those of the front-end chips, the performance of the top CPU is much worse in this regard. The power supply network of a 3D IC consumes twice the power of a single front-end chip network. To make matters worse, the 3D stack doesn't dissipate heat very well, with the hottest part of the bottom chip being almost 2.5 times hotter than a single front-facing CPU. The top CPU is a little cooler, but not by much.

The researchers tested a scenario where a CPU with a back-powered network (gray on the bottom) was paired with another CPU with a front-powered network (top gray) are connected.

Rongmei Chen, a researcher at Imec, said that 3D IC simulation is indeed somewhat unrealistic. Stacking two identical CPUs together is unlikely, while stacking memory with a CPU is much more common. "This comparison is unfair, but it does reflect some potential problems," he said.

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