Linux vcs is a compiled verilog simulator, a tool used to simulate and view waveforms; it is similar to tools such as modelsim and questasim under windows, as well as quartus and vivado simulation operations.
#The operating environment of this tutorial: linux5.9.8 system, Dell G3 computer.
What is linux vcs?
The basic use of VCS tools
VCS is The tools used to simulate and view waveforms under Linux are similar to tools such as modelsim and questasim under Windows, as well as quartus and vivado simulation operations.
1.Basic instructions for vcs
Common instruction suffixes for vcs
Command
Meaning
-l readme.log
is used to compile the information generated Place it in the log file
v2k
is the standard that makes VCS compatible with verilog before 2001
-debug_all
Files required to generate debug
##-f verilog_file.f
You can compile all the source code in the .f file
-R
Run immediately after compilation, that is, execute immediately after compilation is completed
./simv
-Mupdate
When the source file is modified, only the modified **.v* will be recompiled * file, saving compilation time.
-sverilog
Turn on support for
Systemverilog and use it when compiling Systemverilog files.
-timescale=1ns/1ns
Set simulation accuracy
-o simv_file
The executable file generated by compilation is
simv by default. You can use -o to change the executable file name. If you modify it here, you will not use simv but the corresponding o name when executing the simulation.
Common commands for simv
Command
Meaning
./simv -l run.log
Save the execution log file
./simv -gui
Open with graphical interface
2. Example of using vcs
The official tutorial of full adder is used. First, the execution process without using a script is introduced. (1) First execute vcs to add the corresponding full_adder file
Write full_adder.v here first because The tb file needs to call it, so write the called file first. This statement will generate a simv file (if -o simv_file is used, the corresponding file name will be generated). (2) You can use the ./simv file to execute the waveform interface, or you can use the following command to open an interface in the background.
dve &或者
./simv -l run.log -gui
(3) If you execute it with ./simv, you will see the wave file directly. If you use dve &, you need to add the simv file yourself. To view the waveform, select simulator->Setup and add the generated simv file.
run all below, if no time scale is given, an error will be reported here. If there is no error, it means that our function is completely correct. Right-click to add the waveform file and press f to display the waveform. (4) The following four keys function The first one: Track who drives the signal ctrl d The second one: Track the value change of the signal ctrl shift d The third one: Tracking the unknown state The fourth one: Tracking who is used to drive
3.How to write the makefile
The script writing method of vcs can help express express to simulate and obtain waveform files. Among them, .PHONY can specify which keywords correspond to the make operation.
In this way, make vcs executes the vcs statement, make sim executes the simv statement, make dve opens the wave file, and make clean removes some redundant files. Among them, verilog_file.f is a list of files, which can be generated using the following statement, so that all file names ending with v are written to the target file.
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