What is the compilation command of linux system

The compilation command of Linux system is "Make". In Linux systems, make is a very important compilation command. Administrators use it to compile and install many open source tools through the command line. Programmers use it to manage the compilation issues of their large and complex projects. make is used to manage automatic compilation tasks for large programs, automatically determine that a certain part of the program needs to be recompiled, and issue compilation instructions.

#The operating environment of this tutorial: linux7.3 system, Dell G3 computer.

The make command under Linux is one of the most frequently used commands by system administrators and programmers. Administrators use it to compile and install many open source tools through the command line, and programmers use it to manage the compilation problems of their large and complex projects. In this article we will use some examples to discuss the working mechanism behind the make command.

Introduction to Make

make is a utility program for Linux systems. It is used to manage automatic compilation tasks for large programs, automatically determine that a certain part of the program needs to be recompiled, and issue compilation instructions. Although, we most commonly use it in the compilation of C language programs. However, make is not limited to a specific language. Make can be used in any language that can run the compiler through a shell command. In addition, you can even use make to describe any build task where a file needs to be automatically updated after the files it depends on change.

How Make Works

For those who don’t know the mechanics behind it, the make command accepts targets just like command line arguments. These goals are usually stored in special files named "Makefile", and the files also contain operations corresponding to the goals. For more information, read this series of articles on how Makefiles work.

When the make command is executed for the first time, it scans the Makefile to find the target and its dependencies. If these dependencies are themselves targets, continue scanning the Makefile for these dependencies to establish their dependencies, and then compile them. Once the main dependencies are compiled, then the main target is compiled (which is passed in through the make command).

Now, assuming you have modified a certain source file and you execute the make command again, it will only compile the target file related to the source file. Therefore, compiling the final executable file saves a lot of money. time.

>Make command example

The following is the test environment used in this article:

OS —— Ubunut 13.04
Shell —— Bash 4.2.45
Application —— GNU Make 3.81

The following is the content of the project:

$ ls 
anotherTest.c Makefile test.c test.h

The following is the content of the Makefile:

all: test test: test.o anotherTest.o 
    gcc -Wall test.o anotherTest.o -o testtest.o: test.c 
    gcc -c -Wall test.c 

anotherTest.o: anotherTest.c 
    gcc -c -Wall anotherTest.c 

clean: 
    rm -rf *.o test

Now let’s look at some examples of make command applications under Linux:

1 . A simple example

To compile the entire project, you can simply use make or follow the make command with the target all.

$ make 
gcc -c -Wall test.c 
gcc -c -Wall anotherTest.c 
gcc -Wall test.o anotherTest.o -o test

You can see the dependencies created for the first time by the make command and the actual targets.

If you view the contents of the directory again, there are some more .o files and executable files:

$ ls 
anotherTest.c anotherTest.o Makefile test test.c test.h test.o

Now, assume you have made some modifications to the test.c file , reuse make to compile the project:

$ make 
gcc -c -Wall test.c 
gcc -Wall test.o anotherTest.o -o test

You can see that only test.o has been recompiled, but the other Test.o has not been recompiled.

Now clean all the target files and executable file test, you can use the target clean:

$ make clean
rm -rf *.o test$ ls
anotherTest.c Makefile test.c test.h

You can see all. The o file and the executable file test have been deleted.

2. Pass the -B option to make all targets always rebuild

By now, you may have noticed that the make command does not compile those files that have been compiled since the last build. There are no changed files, but if you want to override the default behavior of make, you can use the -B option.

Here is an example:

$ make
make: Nothing to be done for `all’.$ make -B
gcc -c -Wall test.c
gcc -c -Wall anotherTest.c
gcc -Wall test.o anotherTest.o -o test

You can see that although the make command will not compile any files, make -B will force compilation of all files target file and final executable file.

3. Use the -d option to print debugging information

If you want to know what make actually does when it is executed, use the -d option.

This is an example:

$ make -d | more
GNU Make 3.81
Copyright (C) 2006 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.

This program built for x86_64-pc-linux-gnu
Reading makefiles…
Reading makefile `Makefile’…
Updating makefiles….
Considering target file `Makefile’.
Looking for an implicit rule for `Makefile’.
Trying pattern rule with stem `Makefile’.
Trying implicit prerequisite `Makefile.o’.
Trying pattern rule with stem `Makefile’.
Trying implicit prerequisite `Makefile.c’.
Trying pattern rule with stem `Makefile’.
Trying implicit prerequisite `Makefile.cc’.
Trying pattern rule with stem `Makefile’.
Trying implicit prerequisite `Makefile.C’.
Trying pattern rule with stem `Makefile’.
Trying implicit prerequisite `Makefile.cpp’.
Trying pattern rule with stem `Makefile’.
--More--

This is a very long output, you also saw that I used the more command to page by page Page display output.

4. Use the -C option to change the directory

You can provide a different directory path for the make command, and the directory will be switched before searching for the Makefile.

This is a directory, assuming you are in the current directory:

$ ls 
file file2 frnd frnd1.cpp log1.txt log3.txt log5.txt
file1 file name with spaces frnd1 frnd.cpp log2.txt log4.txt

But the Makefile of the make command you want to run is saved in the ../make-dir/ directory, you can Do this:

$ make -C ../make-dir/ 
make: Entering directory `/home/himanshu/practice/make-dir’ 
make: Nothing to be done for `all’. 
make: Leaving directory `/home/himanshu/practice/make-dir

你能看到 make 命令首先切到特定的目录下，在那执行，然后再切换回来。

5. 通过 -f 选项将其它文件看作 Makefile

如果你想将重命名 Makefile 文件，比如取名为 my_makefile 或者其它的名字，我们想让 make 将它也当成 Makefile，可以使用 -f 选项。

make -f my_makefile

通过这种方法，make 命令会选择扫描 my_makefile 来代替 Makefile。

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