what is qpi

What is qpi?

QPI , also known as CSI, Common System Interface, is an architecture that can realize direct interconnection between chips.

QPI Technical Features

QPI is a serial high-speed point-to-point connection protocol based on packet transmission, using differential signals and specialized clocks for transmission. In terms of latency, QPI is almost the same as FSB, but can improve higher access bandwidth. A set of QPI has 20 data transmission lines, as well as clock signals for the transmitter (TX) and receiver (RX).

A QPI data packet contains 80 bits and requires two clock cycles or four transmissions to complete the transmission of the entire data packet (the clock signal rate of QPI is half the transmission rate). Among the 20 bits of data transmitted each time, 16 bits are real and valid data, and the remaining four bits are used for cyclic redundancy check to improve the reliability of the system.

Since QPI is bidirectional, it can also receive data transmitted from the other end while sending. In this way, the total bandwidth of each QPI bus = the number of transmissions per second (i.e., QPI frequency) × the effective number of each transmission Data (i.e. 16bit/8=2Byte) × bidirectional. Therefore, the total bandwidth of QPI frequency 4.8GT/s = 4.8GT/s × 2Byte × 2 = 19.2GB/s, and the total bandwidth of QPI frequency 6.4GT/s = 6.4GT/s × 2Byte × 2 = 25.6GB/s . (bit-bit, Byte-byte, 1Byte=8bit) is more efficient

In addition, another highlight of QPI is that it supports multiple system bus connections, which Intel calls multi-FSB. The system bus will be divided into multiple connections, and the frequency will no longer be single and fixed, and there will be no need to connect through the FSB as before. According to the data throughput requirements of each subsystem of the system, the speed of each system bus connection can also be different. This feature is undoubtedly more flexible than AMD's Hypertransport bus.

What does qpi bring?

QPI (Quick Path Interconnect) - "Quick Path Interconnect", a point-to-point connection technology that replaces the front side bus (FSB). The bandwidth of the 20-bit wide QPI connection can reach astonishing 25.6GB per second, far from comparable to FSB. The first place where QPI can shine is on server platforms that support multiple processors. QPI can be used for interconnection between multiple processors.

1. QPI makes communication more convenient

QPI is an architecture that integrates a memory controller in the processor. It is mainly used for interconnection communication between processors and system components (such as I/O). He abandoned the FSB that has been used for many years. The CPU can directly access memory resources through the memory controller, instead of the previous complicated "front-side bus-Northbridge-memory controller" mode. Moreover, unlike the 4HT3 (4 transmission lines, two for data transmission and two for data reception) connection method used by AMD on mainstream multi-core processors, Intel uses a 4 1 QPI interconnection method (4 for processing processor, 1 designed for I/O), so that each processor of the multi-processor can be directly connected to the physical memory, and each processor can also be interconnected with each other to make full use of different memories, allowing the multi-processor Waiting time is shortened (access delay can be reduced by more than 50%), and only one memory slot can achieve the same bandwidth as a four-way AMD Opteron processor (AMD's processor in the server field, product positioning equivalent to Intel Xeon) .

2. QPI, the peak bandwidth between processors can reach 96GB/s

In Intel's high-end Itanium processor system, the QPI high-speed interconnection method enables the peak bandwidth between CPUs It can reach 96GB/s, and the peak memory bandwidth can reach 34GB/s. This is mainly because QPI adopts a point-to-point design similar to PCI-E, including a pair of lines, which are responsible for data transmission and reception respectively. Each channel can transmit 20bit data. This means that even the earliest QPI standard can achieve a transmission speed of 6.4GT/s - a total bandwidth of 25.6GB/s (twice the 12.8GB/S of FSB 1600MHz). This kind of bandwidth is comparable to AMD's bus solution and can meet the data transmission requirements between CPU and CPU, CPU and chip in the future.

3. Multi-core data transmission does not need to go through the chipset

The QPI bus can realize direct interconnection within the multi-core processor, without the need to connect through the FSB as before. For example, the Nehalem architecture processor for servers has at least 4 sets of QPI transmissions, which can form at least a 4-way high-end server system including 4 processors (that is, 16 computing cores and at least 32 threads operating in parallel). Moreover, under multi-processor operation, each processor can transmit data to each other without going through the chipset, thus greatly improving the overall system performance. With the emergence of future Nehalem architecture processors with integrated memory controllers, PCI-E 2.0 graphics interfaces and even graphics cores, the advantages of the QPI architecture will be further unleashed.

4. The QPI interconnection architecture itself is upgradable

QPI uses series connection for signal transmission, and adopts LVDS (low voltage differential signaling technology), which is mainly used for high-speed digital signal interconnection to make the signal (can transmit at a rate of hundreds of Mbps or more) signal technology, which can ensure stability at high frequencies. QPI has lower latency and a better architecture that will include integrated memory controllers and communication links between system components.

5. QPI bus architecture has reliability and performance

The reliability, practicality and applicability features guarantee the high availability of QPI. Such as link-level cyclic redundancy code verification (CRC). When a clock password failure occurs, the clock can be automatically rerouted to the data channel. QPI also has hot-swappability. The deeply improved micro-architecture, integrated memory controller design and QPI direct technology enable Nehalem to have better execution efficiency. Under the condition of a single thread and the same frequency, Nehalem has even better execution efficiency. Under the condition of a single thread and the same frequency, Nehalem The computing power may be 30% more efficient than the current Penryn architecture at the same power consumption.

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