Why are elementwise additions faster in separate loops than in a single loop, considering cache behavior?

Why are elementwise additions much faster in separate loops than in a combined loop?

Initially, the question was posed regarding the performance difference between elementwise additions performed in a combined loop versus separate loops. However, it was later modified to seek insights into the cache behaviors that lead to these performance variations.

Initial Question

Question:

Why are elementwise additions significantly faster in separate loops than in a combined loop?

Answer:

Upon further analysis, it is believed that this behavior is caused by data alignment issues with the four pointers used in the operation, potentially resulting in cache bank/way conflicts. Specifically, it is likely that the arrays are allocated on the same page line, leading to accesses within each loop falling on the same cache way. This is less efficient than distributing the accesses across multiple cache ways, which is possible when the arrays are allocated separately.

Cache Behavior Analysis

Question:

Could you provide some solid insight into the details that lead to the different cache behaviors as illustrated by the five regions in the graph?

Answer:

Region 1: The dataset is so small that performance is dominated by overhead, such as looping and branching, rather than cache behavior.

Region 2: Previously attributed to alignment issues, further analysis suggests that the performance drop in this region needs further investigation. Cache bank conflicts could still be a factor.

Region 3: The data size exceeds the L1 cache capacity, leading to performance limitations imposed by the L1 to L2 cache bandwidth.

Region 4: The performance penalty observed in the single-loop version is likely due to false aliasing stalls in the processor's load/store units caused by the alignment of the arrays. False aliasing occurs when the processor speculatively executes load operations and encounters a second load to the same address with a different value. In this case, the processor must discard the speculative load and reload the correct value, leading to a performance penalty.

Region 5: At this point, the data size exceeds the capacity of both the L1 and L2 caches, resulting in performance limitations imposed by memory bandwidth.

Architectural Differences

Question:

It might also be interesting to point out the differences between CPU/cache architectures, by providing a similar graph for these CPUs.

Answer:

The provided graph represents data collected from two Intel Xeon X5482 Harpertown processors at 3.2 GHz. Similar tests on other architectures, such as the Intel Core i7 870 @ 2.8 GHz and the Intel Core i7 2600K @ 4.4 GHz, produce graphs that exhibit similar regions, although the specific performance values may vary. These variations can be attributed to differences in cache sizes, memory bandwidth, and other architectural features.

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