Why Does `std::atomic` Use XCHG to Ensure Sequential Consistency in Stores?

XCHG's Role in Ensuring Sequential Consistency in std::atomic Stores

While it may seem intuitive to employ a regular store followed by a read/write memory barrier to achieve sequential consistency, std::atomic's store with sequential consistency (seq_cst) order instead utilizes XCHG. This approach is justified by the specific characteristics of XCHG in x86 and x86_64 architectures.

Atomic RMW and Full Memory Barriers

On x86 architectures, atomic read-modify-write (RMW) operations, such as XCHG, inherently act as full memory barriers. The implicit lock prefix on XCHG enforces a global order, ensuring that the load and store operations it performs cannot be separated by buffering or load-load reordering.

Sequential Consistency vs. Sequential Release

Ordinary store operations on x86 possess release semantics, which allow them to reorder with subsequent operations, including acquire loads. To enforce sequential consistency, a sequential release barrier, rather than a release barrier alone, would be necessary.

Performance Considerations

Choosing between MFENCE and XCHG for implementing seq_cst stores involves performance trade-offs. While MFENCE blocks out-of-order execution on Intel Skylake and subsequent architectures, XCHG does not. This difference can impact surrounding code execution. Other factors, such as cache state and thread contention, may also affect performance.

Compiler and Kernel Recommendations

Recent versions of GCC and modern compilers favor XCHG over MFENCE for seq_cst stores on most platforms. The Linux kernel employs XCHG for atomic seq_cst stores, while it uses both XCHG and MFENCE for different types of memory barriers.

Implicit Memory Barriers in x86

The statement implying that x86 and x86_64 stores possess an implicit acquire fence is incorrect. Stores on these architectures have release semantics by default. For acquiring semantics, an acquire operation must be explicitly specified.

Conclusion

The use of XCHG in std::atomic's seq_cst stores guarantees sequential consistency on x86 and x86_64 platforms by leveraging the full memory barrier properties inherent in RMW operations. Other options, such as MFENCE, may provide weaker guarantees or different performance characteristics depending on the specific hardware and operating conditions.

The above is the detailed content of Why Does `std::atomic` Use XCHG to Ensure Sequential Consistency in Stores?. For more information, please follow other related articles on the PHP Chinese website!