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Why does std::atomic's store use XCHG when sequential consistency is requested?
While a sequential-consistency store operation may appear at first as something that can be implemented using a simple store instruction followed by a memory barrier, using XCHG (with an implied lock prefix) offers a more optimal solution.
XCHG and Sequential Consistency
On x86 and x86_64 architectures, XCHG provides both a memory exchange and a full memory barrier, ensuring sequential ordering of memory operations. This makes it an effective way to implement sequential consistency stores.
Limitations of Regular Store Instructions
A regular store instruction alone, such as MOV, can not guarantee sequential consistency. It only provides release semantics, which allows it to be reordered with later operations, including acquire loads.
Performance Considerations
While both MFENCE and XCHG can be used to implement sequential-consistency stores, they exhibit different performance characteristics on various CPUs. On certain CPUs, MFENCE can stall out-of-order execution of neighboring instructions. In contrast, XCHG may be more efficient for single-threaded operations or when the cached line is hot in L1 cache.
Compiler and Kernel Practices
Various compilers and operating systems prefer different approaches for implementing sequential-consistency stores. GCC historically used MOV MFENCE, while other compilers and the Linux kernel employ XCHG.
Additional Notes
It's important to note that:
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