How do `std::hardware_destructive_interference_size` and `std::hardware_constructive_interference_size` relate to L1 cache line size and what are their use cases?

Understanding std::hardware_destructive_interference_size and std::hardware_constructive_interference_size

Introduction:

C 17 introduced two constants, std::hardware_destructive_interference_size and std::hardware_constructive_interference_size, to facilitate alignment and layout of data structures for optimal performance on different hardware architectures.

How are these constants related to the L1 cache line size?

These constants are intended to provide an approximation of the L1 cache line size for the target architecture.

• Destructive interference: std::hardware_destructive_interference_size provides a value that can be used as an offset between objects to avoid false-sharing, a situation where data from two or more objects is placed on the same cache line, causing performance degradation due to contention.
• Constructive interference: std::hardware_constructive_interference_size provides a value that can be used as a limit on the combined memory footprint and base alignment of objects to promote true-sharing, where data from different objects is placed on the same cache line to improve performance.

Is there a good example that demonstrates their use cases?

Consider the following example:

struct CacheOptimizedStruct {
  alignas(std::hardware_constructive_interference_size) int a;
  alignas(std::hardware_constructive_interference_size) int b;
};

int main() {
  CacheOptimizedStruct data;
  // Accessing data.a and data.b in a tight loop will likely benefit from better cache locality.
}

In this example, the alignas attribute uses the constants to ensure that data.a and data.b have optimal alignment and memory layout for true-sharing.

Both are defined static constexpr. Is that not a problem if you build a binary and execute it on other machines with different cache line sizes?

Yes, this can be an issue. The constants are not guaranteed to provide precise cache line sizes for all target machines.

However, you can define your own constants or macros to provide more accurate values based on system-specific information, such as:

#ifdef KNOWN_L1_CACHE_LINE_SIZE
  constexpr std::size_t cache_line_size = KNOWN_L1_CACHE_LINE_SIZE;
#else
  constexpr std::size_t cache_line_size = std::hardware_destructive_interference_size;
#endif

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