Understanding the Makefile (Example with C language).

A Makefile is a file used by the make tool to automate the compilation of programs. Here are the standard rules and best practices for writing an effective Makefile:

Basic Structure of a Makefile

1. Target: What you want to build (e.g. an executable file).
2. Prerequisites: The files necessary to build the target (e.g. source files).
3. Rule: The command to execute to create the target.

Simple Example

target: prerequisites
    command

Standard Rules

1. Default rule: The first target in the Makefile is the one that will be built by default.

2. Compiling source files:

   • Use variables for compilers and options.
   • Example:

   CC = gcc
   CFLAGS = -Wall -g
   SOURCES = main.c utils.c
   OBJECTS = $(SOURCES:.c=.o)
   TARGET = mon_programme

   $(TARGET): $(OBJECTS)
       $(CC) -o $@ $^

   %.o: %.c
       $(CC) $(CFLAGS) -c $



<ol>
<li>
<strong>Phonies</strong>: Uses .PHONY for targets that are not files.
</li>
</ol>

<pre class="brush:php;toolbar:false">   .PHONY: clean
   clean:
       rm -f $(OBJECTS) $(TARGET)

1. Variables: Uses variables to simplify the management of paths and options.

   CC = gcc
   CFLAGS = -Wall

1. Dependency management: Uses implicit rules and patterns to reduce repetition.

2. Automatic dependencies: You can generate dependencies automatically for .o files.
   

   -include $(OBJECTS:.o=.d)

Full Example

Here is a complete Makefile example:

# Variables
CC = gcc
CFLAGS = -Wall -g
SOURCES = main.c utils.c
OBJECTS = $(SOURCES:.c=.o)
TARGET = mon_programme

# Règle par défaut
all: $(TARGET)

# Lien de l'exécutable
# $@ -> $(TARGET)
# $^ -> $(OBJECTS)
$(TARGET): $(OBJECTS)
    $(CC) -o $@ $^

# Compilation des fichiers .c en .o
# $ Premier element des pr
%.o: %.c
    $(CC) $(CFLAGS) -c $



<h3>
  
  
  Good Practices
</h3>

<ol>
<li><p><strong>Indent with tabs</strong>: Commands in rules should be indented with tabs, not spaces.</p></li>
<li><p><strong>Comment code</strong>: Uses comments to explain sections of the Makefile.</p></li>
<li><p><strong>Group files</strong>: If your project contains multiple files, organize them into subdirectories and use variables to manage paths.</p></li>
<li><p><strong>Use implicit rules</strong>: Take advantage of make's built-in rules to avoid rewriting common rules.</p></li>
</ol>

<h3>
  
  
  Why use .PHONY?
</h3>

• Avoid conflicts: If a file with the same name as a target exists, make will think that the target is up to date and will not execute the associated commands. .PHONY avoids this.

• Improved performance:Phony targets are always considered "to do", which can improve the speed of execution of associated commands.

Why use %.o:%c for compilation?

• Efficiency: Using %.o:%c allows you to benefit from make optimization to only recompile what is necessary.

• Practical: For larger projects, %.o:%c is much more suitable.

Conclusion

A well-structured Makefile makes project management easier and avoids compilation errors. By following these rules and best practices, you can create an efficient and maintainable Makefile.

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